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4-557 product description ordering information typical applications features functional block diagram rf micro devices, inc. 7628 thorndike road greensboro, nc 27409, usa tel (336) 664 1233 fax (336) 664 0454 http://www.rfmd.com optimum technology matching? applied si bjt gaas mesfet gaas hbt si bi-cmos sige hbt si cmos ingap/hbt gan hemt sige bi-cmos rf out rf in nc nc nc nc 12 11 10 4 5 6 1 2 3 9 8 7 gnd gnd gnd gnd gnd gnd RF3305 broadband high linearity amplifier ? basestation applications ? cellular and pcs systems ? wll, w-cdma systems ? final pa for low-power applications the RF3305 is a high-efficiency gaas heterojunction bipolar transistor (hbt) amplifier packaged in a low-cost surface-mount package. this amplifier is ideal for use in applications requiring high-linearity and low noise figure over the 300mhz to 3ghz frequency range. the RF3305 operates from a single 5v power supply. the 3mmx3mm footprint is compatible with standard sot89 packages. ? 300mhz to 3ghz ? +40dbm output ip3 ? 12.5db gain at 2.0ghz ? +23dbm p1db ? 3.0db typical noise figure at 2.0ghz ? single 5v power supply RF3305 broadband high linearity amplifier RF3305 pcba fully assembled evaluation board 0 rev a15 031120 3.00 3.00 2.75 sq -b- -a- 3 1 2 plcs 0.10 c a 2 plcs 0.10 c b 2 plcs 0.10 c a 2 plcs 0.10 c b shaded lead is pin 1. dimensions in mm. -c- 12 max seating plane 0.05 c 0.20 ref. 0.90 0.85 0.05 0.00 0.60 0.24 typ 0.10 c ab m 0.35 0.30 pin 1 id r0.20 1.90 1.60 0.45 0.35 0.375 0.275 0.65 1.15 0.85 package style: qfn, 12-pin, 3x3 preliminary 9
preliminary 4-558 RF3305 rev a15 031120 absolute maximum ratings parameter rating unit rf input power +20 dbm device voltage -0.5 to +6.0 v device current 250 ma operating temperature -40 to +85 c storage temperature -40 to +150 c junction temperature +225 c parameter specification unit condition min. typ. max. overall ac specificat ions (2ghz) v cc =5v, rf in =-10dbm, freq=2.0ghz, with 2ghz application schematic. frequency 300 3000 mhz gain (small signal) 11.0 12.5 db f=2ghz input return loss 15 db f=2ghz output return loss 15 db f=2ghz output ip3 +36.5 +40.0 dbm f 1 = 1.99ghz, f 2 =2.00ghz, p in =-5dbm output p1db +17.0 +23.0 dbm noise figure 3.0 db ac specifications (900mhz) v cc =5v, rf in =-10dbm, freq=900mhz, with 900mhz application schematic. frequency 300 3000 mhz gain (small signal) 17 18 db input return loss 20 db output return loss 20 db output ip3 38 41 dbm f 1 = 900mhz, f 2 =901mhz, p in =-10dbm output p1db 20 25 dbm noise figure 2.5 db thermal i cc =150ma, p diss =750mw. (see note.) theta jc 88 c/w maximum measured junction temperature at dc bias con- ditions 146 c t amb =+85c mean time to failure 795 years t amb =+85c dc specifications device voltage 4.5 5.0 5.5 v i cc =150ma operating current range 120 150 170 ma v cc =5v note: the RF3305 must be operated at or below 150ma in order to achieve the thermal performance listed above. while the RF3305 may be operated at higher bias currents, 150ma is the recommended bias to ensure the highest possible reliability and electrica l performance. caution! esd sensitive device. rf micro devices believes the furnished information is correct and accurate at the time of this printing. however, rf micro devices reserves the right to make changes to its products without notice. rf micro devices does not assume responsibility for the use of the described product(s).
preliminary 4-559 RF3305 rev a15 031120 pin function description interface schematic 1nc not internally connected. 2nc not internally connected. 3rf in rf input pin. this pin is not internally dc-blocked. a dc blocking capacitor, suitable for the frequency of operation, should be used in most applications. 4gnd ground. 5gnd ground. 6gnd ground. 7rf out rf output and bias pin. for biasing, an rf choke is needed. because dc is present on this pin, a dc blocking capacitor, suitable for the fre- quency of operation, should be used in most applications. see applica- tion schematic for configuration and value. 8nc not internally connected. 9nc not internally connected. 10 gnd ground. 11 gnd ground. 12 gnd ground. pkg base gnd ground connection. vcc rf in vcc rf out
preliminary 4-560 RF3305 rev a15 031120 typical application schematic for 2ghz evaluation board schematic for 2ghz rf in rf out 100 pf + 1 f + v cc 82 nh 2 pf 100 pf 1.8 pf v cc 12 11 10 4 5 6 1 2 3 9 8 7 3.6 nh l1 82 nh vcc 50 ? strip j2 rf out 50 ? strip j1 rf in p1 1 2 3 con3 p1-1 vcc gnd gnd c5 2 pf c1 100 pf c2 1.8 pf vcc c4 1 f + c3 100 pf l2 3.6 nh 12 11 10 4 5 6 1 2 3 9 8 7
preliminary 4-561 RF3305 rev a15 031120 typical application schematic for 900mhz evaluation board schematic for 900mhz rf in rf out 1 f + 100 nh 22 pf 5.0 pf 6 pf v cc 12 11 10 4 5 6 1 2 3 9 8 7 8.7 nh 4.7 nh 1000 pf p1 1 2 3 con3 p1-1 vcc gnd gnd c5 1 f + l2 100 nh c3 22 pf 5.0 pf c2 6 pf v cc 12 11 10 4 5 6 1 2 3 9 8 7 l3 8.7 nh 4.7 nh c4 1000 pf j1 rf in j2 rf out
preliminary 4-562 RF3305 rev a15 031120 evaluation board layout for 2ghz board size 1.195? x 1.000? board thickness 0.033?, board material fr-4 note: a small amount of ground inductance is required to achieve datasheet performance. the necessary inductance may be generated by ensuring that no ground vias are placed directly below the footprint of the part. evaluation board layout for 900mhz board size 1.195? x 1.000? board thickness 0.033?, board material fr-4 note: a small amount of ground inductance is required to achieve datasheet performance. the necessary inductance may be generated by ensuring that no ground vias are placed directly below the footprint of the part.
preliminary 4-563 RF3305 rev a15 031120 noise figure versus frequency across temperature v cc = 5.0v (2ghz application circuit) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1750.0 1800.0 1850.0 1900.0 1950.0 2000.0 2050.0 2100.0 2150.0 2200.0 frequency (mhz) noise figure (db) -40c 25c 85c gain versus frequency across temperature v cc = 5.0v (2ghz application circuit) 4.0 6.0 8.0 10.0 12.0 14.0 16.0 1750.0 1800.0 1850.0 1900.0 1950.0 2000.0 2050.0 2100.0 2150.0 2200.0 frequency (mhz) gain (db) -40c 25c 85c oip3 versus frequency across temperature v cc = 5.0v (2ghz application circuit) 36.0 36.5 37.0 37.5 38.0 38.5 39.0 39.5 40.0 40.5 41.0 1750.0 1800.0 1850.0 1900.0 1950.0 2000.0 2050.0 2100.0 2150.0 2200.0 frequency (mhz) oip3 (dbm) -40c 25c 85c i cc versus v cc across temperature 90.0 100.0 110.0 120.0 130.0 140.0 150.0 160.0 170.0 180.0 190.0 4.34.54.85.05.35.55.8 v cc (v) i cc (ma) -40c 25c 85c p1db versus frequency across temperature v cc = 5.0v (2ghz application circuit) 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 26.0 1750.0 1800.0 1850.0 1900.0 1950.0 2000.0 2050.0 2100.0 2150.0 2200.0 frequency (mhz) p1db (dbm) -40c 25c 85c mttf versus junction temperature (60% confidence interval) 1.0 10.0 100.0 1000.0 10000.0 100000.0 1000000.0 100.0 125.0 150.0 175.0 200.0 junction temperature (c) mttf (years)
preliminary 4-564 RF3305 rev a15 031120 noise figure versus frequency across temperature, v cc =5.0v (900mhz application circuit) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 750.0 800.0 850.0 900.0 950.0 1000.0 1050.0 frequency (mhz) noise figure (db) -40c 25c 85c gain versus frequency across temperature v cc =5.0v (900mhz application circuit) 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 750.0 800.0 850.0 900.0 950.0 1000.0 1050.0 frequency (mhz) gain (db) -40c 25c 85c oip3 versus frequency across temperature vcc=5.0v (900mhz application circuit) 33.0 34.0 35.0 36.0 37.0 38.0 39.0 40.0 41.0 42.0 43.0 750.0 800.0 850.0 900.0 950.0 1000.0 1050.0 frequency (mhz) oip3 (dbm) -40c 25c 85c p1db versus frequency across temperature v cc =5.0v (900mhz application circuit) 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 750.0 800.0 850.0 900.0 950.0 1000.0 1050.0 frequency (mhz) p1db (dbm) -40c 25c 85c
preliminary 4-565 RF3305 rev a15 031120 0 1.0 1.0 -1.0 10.0 1 0 . 0 - 1 0 . 0 5.0 5 . 0 - 5 . 0 2.0 2 . 0 - 2 . 0 3.0 3 . 0 - 3 . 0 4.0 4 . 0 - 4 . 0 0.2 0 . 2 - 0 . 2 0.4 0 . 4 - 0 . 4 0.6 0 . 6 - 0 . 6 0.8 0 . 8 - 0 . 8 RF3305 s11 swp max 3300mhz swp min 300mhz 3.3 ghz 300 mhz s11 0 1.0 1.0 -1.0 10.0 1 0 . 0 - 1 0 . 0 5.0 5 . 0 - 5 . 0 2.0 2 . 0 - 2 . 0 3.0 3 . 0 - 3 . 0 4.0 4 . 0 - 4 . 0 0.2 0 . 2 - 0 . 2 0.4 0 . 4 - 0 . 4 0.6 0 . 6 - 0 . 6 0.8 0 . 8 - 0 . 8 RF3305 s22 swp max 3300mhz swp min 300mhz 300 mhz 3.3 ghz s22
preliminary 4-566 RF3305 rev a15 031120 pcb design requirements pcb surface finish the pcb surface finish used for rfmd?s qualification process is electroless nickel, immersion gold. typical thickness is 3 inch to 8 inch gold over 180 inch nickel. pcb land pattern recommendation pcb land patterns are based on ipc-sm-782 standards when possible. the pad pattern shown has been developed and tested for optimized assembly at rfmd; however, it may require some modifications to address company specific assembly processes. the pcb land pattern has been developed to accommodate lead and package tolerances. pcb metal land mask pattern a = 0.59 x 0.32 (mm) typ. 0.65 (mm) typ. pin 1 0.40 (mm) typ. 0.95 (mm) typ. 0.65 (mm) typ. 3.20 (mm) typ. a a a a a a 0.80 (mm) typ. 1.00 (mm) 2.60 (mm) 1.30 (mm) typ. 0.30 (mm) typ. 2.20 (mm) typ. 1.00 (mm) typ. 0.70 (mm) typ. figure 1. pcb metal land pattern (top view)
preliminary 4-567 RF3305 rev a15 031120 pcb solder mask pattern liquid photo-imageable (lpi) solder mask is recommended. th e solder mask footprint will match what is shown for the pcb metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. the center-grounding pad shall also have a solder mask clearance. expansion of the pads to create solder mask clearance can be provided in the master data or requested from the pcb fabrication supplier. thermal pad and via design the pcb metal land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bot- tom of the device. thermal vias are required in the pcb layout to effectively conduct heat away from the package. the via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. the via pattern used for the rfmd qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. if micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. note: a small amount of ground inductance is required to achieve data sheet performance. the necessary inductance may be generated by ensuring that no ground vias are placed directly below the footprint of the part. a = 0.72 x 0.45 (mm) typ. pin 1 a a a a a a 3.32 (mm) typ. 0.65 (mm) typ. 1.01 (mm) typ. 0.72 (mm) typ. 1.15 (mm) 2.27 (mm) typ. 1.05 (mm) typ. 0.75 (mm) typ. 0.41 (mm) typ. 1.30 (mm) typ. 2.60 (mm) 0.65 (mm) typ. 0.45 (mm) typ. figure 2. pcb solder mask (top view)
preliminary 4-568 RF3305 rev a15 031120

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